Ensuring the integrity of data processed by a data processing system such as a computer or like electronic device is critical for the reliable operation of such a system. Data integrity is of particular concern, for example, in fault tolerant applications such as servers, databases, scientific computers, and the like, where any errors whatsoever could jeopardize the accuracy of complex operations and/or cause system crashes that affect large numbers of users.
Data integrity issues are a concern, for example, for many solid state memory arrays such as those used as the main working storage repository for a data processing system. Solid state memory arrays are typically implemented using multiple integrated circuit memory devices such as static or dynamic random access memory (SRAM or DRAM) devices, and are controlled via memory controllers typically disposed on separate integrated circuit devices and coupled thereto via a memory bus.
A significant amount of effort has been directed toward detecting and correcting errors in memory devices during power up of a data processing system, as well as during the normal operation of such a system. It is desirable, for example, to enable a data processing system to, whenever possible, correct any detected problems automatically, without requiring a system administrator or other user to manually perform any repairs. It is also desirable for any such corrections to be performed in such a fashion that the system remains up and running. Often such characteristics are expensive and only available on complex, high performance data processing systems. Furthermore, in many instances, many types of errors go beyond the ability of a conventional system to do anything other than “crash” and require a physical repair before normal device operation can be restored.
One such type of error that has traditionally presented difficulties in conventional data processing systems is a failure in the interface of a memory device. In many DRAM memory devices, for example, when a memory device is powered up, a certain sequence of events is expected and required for appropriate operation. Typically, once power is applied, clocks are applied, followed by initialization, and then initiation of a periodic refresh operation. However, if some portion of the interface for the memory device is broken (e.g., due to a bad clock input, a bad address or command input, etc.), it may not be possible to complete this sequence of events.
Many integrated circuit devices or chips support a test scan interface, as well as on-board Built-In Self-Test (BIST) logic, that assist in diagnosing, and sometimes correcting, errors in a device. One widely used test scan interface is the Joint Test Action Group (JTAG) test scan interface, which relies on a set of five signals to communicate diagnostic data to or from an integrated circuit device. On-board scan registers are architected into the integrated circuit device to either insert or capture data at various internal nodes in a circuit. Arrays may be tested using Array BIST (ABIST) circuitry, while logic circuitry may be tested using Logical BIST (LBIST) circuitry, with both types of circuitry capable of being interfaced with a JTAG interface for communication with an external device.
Conventional JTAG interfaces, however, require a set of dedicated interconnects (i.e., pins, contact pads, balls, etc.) on an integrated circuit device. On many integrated circuit devices, the addition of a set of JTAG interconnects does not present a problem. However, for many devices, particularly most memory devices, there is a strong reluctance to increase the number of interconnects beyond those required for the functional interfaces for the devices, often due to extremely tight cost concerns. Existing memory device standards, including, for example, SDRAM standards such as DDR, DDR2, and FB-DIMM, do not support any dedicated JTAG or other diagnostic interconnects.
As such, conventional memory devices have not provided support for JTAG or other diagnostic interfaces, and thus remain extremely susceptible to certain types of errors such as memory interface errors on the devices that inhibit communication with a memory controller. Furthermore, given cost constraints, it is unlikely that dedicated diagnostic interfaces would be acceptable to most memory device standards bodies. A significant need has therefore arisen for a manner of providing a diagnostic interface on a memory device in a cost effective, reliable and acceptable manner.